| Instructor: Peter Breznay | Location: MAC 122 | |
| Office Hours: TR 10:30-11:30 pm TR 5:30-6:30 pm | Office: CH C324 | |
| and by appointment | Phone: 465-2170 |
Texts:
William Stallings. Computer Organization and Architecture, (7th edition) Prentice Hall 2008
On Reserve:
Patterson & Hennessey. Computer Organization and Design, McGraw-Hill 2001
| CPU Animation: | Central Queensland University CPU Animation | |
| Computing History: | Difference Engine and all |
| Topic | Content Description |
|---|---|
| 1 | History and overview of Computer Functions: History of computers, components (hardware/software, memory, CPU, registers, I/O devices), Von Neumann machine operation, instruction cycle & interrupts, performance ratings, evolutionary trends. Chapters 1 & 2; Reserve book (Chapter 2) |
| 2 | Bus Organization: Buses (Address, data, & control), performance, arbitration, data transfer; PCI architecture. Chapter 3. |
| 3 | Digital Logic and Circuit Design: Digital logic, Boolean Algebra, combinational circuits, decoders, multiplexers, circuit design, Karnaugh maps, programmed logic arrays, read only memory, binary adders, seven-segment displays. Appendix A.1-A.3. |
| 4 | Memory: Cache, Primary, and Secondary Systems: Flip-flops, random-access memory, chip organization, cache memory (direct, associative, and hybrid), disks, tapes, RAID scheme, and optical memory. Appendix A.4, Chapters 4, 5 & 6. 1st EXAM |
| 5 | Data Representation: Binary number system; integer and floating point data; two's complement and floating point arithmetic, character codes. Chapter 9. |
| 6 | Machine logic: Machine and assembly language instructions, addressing modes, example code from PC to include control, branching, loops, procedure calls, and interfacing with a high level language. Chapters 10 & 11; handouts. 2nd EXAM |
| 7 | Central processing Unit: Processor and register organization, pipelining, branch penalty and solutions; NOOPs, pre-fetching, branch prediction. Chapter 12. |
| 8 | Alternative architectures. Reduced Instruction Set Computers (RISC), Superscalar processors, parallel architectures, cache coherency. Parts of chapters 13, 14, and 18. |
| 9 | Microprogrammed control: Microinstructions, hardwire vs. microprogrammed control, vertical and horizontal microinstructions. Chapters 16 and 17 (handouts). FINAL EXAM. |